Title :
A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS
Author :
Reutemann, Robert ; Ruegg, Martin ; Keyser, F. ; Bergkvist, John ; Dreps, Daniel ; Toifl, Thomas ; Schmatz, Martin
Author_Institution :
Miromico, Zurich, Switzerland
Abstract :
A 23 (22 data+1 clk) lane source-synchronous RX PHY for server systems is realized in 65 nm CMOS supporting FB-DIMM 2 and QP11.0 multiple link protocols at 4.8-6.4 Gb/s. To minimize jitter, either a poly-phase filter or clean-up PLL can be selected for l/Q clock generation. Power consumption of 4.5 mW/Gb/s is achieved in the product-level design by a pulsed CDR using dithering to avoid excess jitter.
Keywords :
CMOS integrated circuits; clock and data recovery circuits; jitter; phase locked loops; receivers; synchronisation; CMOS; dithering; jitter; l/Q clock generation; lane source-synchronous link RX core; multiple link protocols; optional cleanup PLL; poly-phase filter; pulsed CDR; server systems; Bandwidth; Clocks; Crosstalk; Frequency; Jitter; Logic; Phase locked loops; Pulse amplifiers; Sampling methods; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-6033-5
DOI :
10.1109/ISSCC.2010.5434008
