Title :
Reconfigurable synchronized dataflow processor
Author :
Sasaki, Hiroshi ; Maruyama, Hitoshi ; Kobayashi, Hiroaki ; Nakamura, Tadao ; Tsukioka, Hideaki ; Shoji, Nobuyoshi
Author_Institution :
Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan
Abstract :
This paper describes the design and implementation of a reconfigurable synchronized dataflow processor (RSDP). The RSDP can configure its hardware to directly represent dataflow graphs (DFGs) of applications. Data are processed while they flow along application-specific datapaths in the RSDP. We have designed three DFGs for benchmarking and evaluated their performance on an RSDP board. The results show that the RSDP running at relatively lower frequency can achieve a competitive performance with a general-purpose processor.
Keywords :
CMOS digital integrated circuits; data flow computing; data flow graphs; large scale integration; microprocessor chips; performance evaluation; reconfigurable architectures; synchronisation; 0.35 micron; 30 MHz; CMOS LSI chip; DFG; application-specific datapaths; dataflow graphs; reconfigurable synchronized dataflow processor; Application software; Computational modeling; Delay; Filters; Frequency synchronization; Functional programming; Hardware; Integrated circuit interconnections; Read-write memory; Registers;
Conference_Titel :
Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific
Conference_Location :
Yokohama, Japan
Print_ISBN :
0-7803-5973-9
DOI :
10.1109/ASPDAC.2000.835062
