DocumentCode
1888973
Title
A 47×10Gb/s 1.4mW/(Gb/s) parallel interface in 45nm CMOS
Author
O´Mahony, F. ; Kennedy, Jessie ; Jaussi, J.E. ; Balamurugan, Ganesh ; Mansuri, Mozhgan ; Roberts, Clive ; Shekhar, Shashi ; Mooney, Randy ; Casper, Bryan
Author_Institution
Intel, Hillsboro, OR, USA
fYear
2010
fDate
7-11 Feb. 2010
Firstpage
156
Lastpage
157
Abstract
A 47 × 10 Gb/s chip-to-chip interface consuming 660 mW is demonstrated in 45 nm CMOS. A dense interconnect topology allows clocking to be shared across multiple lanes to reduce power. Receiver power is reduced by 93% during standby and an integrated wake-up timer indicates that all lanes return reliably to active mode in < 5 ns. The active circuitry occupies 3.2 mm2.
Keywords
CMOS integrated circuits; integrated circuit interconnections; network topology; transceivers; CMOS; active circuitry; chip-to-chip interface; dense interconnect topology; integrated wake-up timer; parallel interface; power 660 mW; receiver power; transceiver; Aggregates; Bandwidth; Clocks; Delay; Integrated circuit interconnections; LAN interconnection; Packaging; Time measurement; Timing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
978-1-4244-6033-5
Type
conf
DOI
10.1109/ISSCC.2010.5434009
Filename
5434009
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