A floating point arithmetic unit for a static scheduling and compiler oriented multiprocessor system ASCA

Author

Kawaguchi, Takahiro ; Suzuki, Takayuki ; Amano, Hideharu

Author_Institution

Dept. of Comput. Sci., Keio Univ., Yokohama, Japan

fYear

2000

fDate

9-9 June 2000

Firstpage

31

Lastpage

32

Abstract

We describe a floating point arithmetic unit (FPU) which supports static scheduling by automatic parallelizing compiler. This FPU designed to work with 50 MHz clock with the assistance of EDA synthesis and layout tools. Under the clock rate condition, it appears that this FPU requires about 120,000 gates and marks 8.2 MFLOPS with the clock level simulations.

Keywords

CMOS logic circuits; floating point arithmetic; multiprocessing systems; parallelising compilers; processor scheduling; 0.6 micron; 50 MHz; 8.2 MFLOPS; MAPLE FPU; automatic parallelizing compiler; clock level simulations; clock rate condition; compiler oriented multiprocessor system; floating point arithmetic unit; static scheduling; Clocks; Concurrent computing; Degradation; Electronic design automation and methodology; Floating-point arithmetic; Graphics; Hardware design languages; Multiprocessing systems; Pipelines; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific

Conference_Location

Yokohama, Japan

Print_ISBN

0-7803-5973-9

Type

conf

DOI

10.1109/ASPDAC.2000.835064

Filename

835064