Title :
A 16-bit redundant binary multiplier using low-power pass-transistor logic SPL
Author :
SAKAMOTO, Hirofumi ; Ochi, Hiroyuki ; UDA, Ken´ichiro ; Taki, Kazuo ; Lee, Bu-Yeol ; TSUDA, Takao
Author_Institution :
Dept. of Comput. Eng., Hiroshima City Univ., Japan
Abstract :
We have designed a 18-bit redundant binary multiplier using pass-transistor logic SPL on a 0.35 /spl mu/m technology. Number of transistors is 12,349, and area is 1322 /spl mu/m/spl times/332 /spl mu/m. Measured power dissipation and maximum delay at T=25/spl deg/C and VDD=3.3 V are 33.7 mW/100 MHz and 7.4 nsec, respectively.
Keywords :
CMOS logic circuits; digital arithmetic; integrated circuit design; logic design; low-power electronics; multiplying circuits; redundancy; 0.35 micron; 16 bit; 3.3 V; 7.4 ns; CMOS IC; low-power pass-transistor logic; redundant binary multiplier; Adders; Algorithm design and analysis; Binary decision diagrams; Circuit synthesis; Delay; Logic circuits; Logic design; MOS devices; Power dissipation; Power measurement;
Conference_Titel :
Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific
Conference_Location :
Yokohama, Japan
Print_ISBN :
0-7803-5973-9
DOI :
10.1109/ASPDAC.2000.835065
