A hardware simulation engine based on decision diagrams

Author

Iguchi, Yukihiro ; Matsuura, Munehiro ; Sasao, Tsutomu ; Iseno, Atsumu

Author_Institution

Dept. of Comput. Sci., Meiji Univ., Kawasaki, Japan

fYear

2000

fDate

9-9 June 2000

Firstpage

73

Lastpage

76

Abstract

A hardware logic simulation engine based on decision diagrams is presented. For the data structure of the engine, we propose PMDDs (Paged reduced ordered Multi-valued Decision Diagrams). A unit of this engine consists of memory (RAMs) and control circuits: RAMs store the PMDD data, and the control circuits trace the edges according to the input vectors. The engine consists of several units, and is accelerated by pipelining. Experimental results using a prototype are shown.

Keywords

decision diagrams; logic simulation; pipeline processing; ISCAS benchmark circuits; PMDDs; RAMs; control circuits; data structure; decision diagrams; edge tracing; hardware logic simulation engine; input vectors; memory circuits; paged reduced ordered multi-valued decision diagrams; pipelining; Binary decision diagrams; Boolean functions; Circuit simulation; Computational modeling; Computer science; Computer simulation; Data structures; Engines; Hardware; Logic;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific

Conference_Location

Yokohama, Japan

Print_ISBN

0-7803-5973-9

Type

conf

DOI

10.1109/ASPDAC.2000.835073

Filename

835073