An interconnect topology optimization by a tree transformation

Since interconnect delay has become the dominating factor in circuit performance, demands for a good delay-minimization router are very high. In this paper, we propose two algorithms to find an interconnect tree of a net which minimizes a weighted sum /spl tau/ of delays to all sinks, where the weight assigned to a sink represents a criticality of the delay to the sink. The algorithms start from a Steiner tree and repeat a tree transformation as monitoring the change of /spl tau/. We also show some experimental results to evaluate the performance of the algorithms.