A software-implemented fault-tolerant technique for microprocessor controllers

Author

Wingate, G.A.S. ; Preece, Clive

Author_Institution

ICI Eng., Billingham, UK

fYear

1993

fDate

26-28 Jan 1993

Firstpage

449

Lastpage

457

Abstract

A fault-tolerant technique implemented transparently on application software is presented to detect invalid branches. A preliminary assessment is made using experiments that emulate and physically inject faults into example programs on 8-b Motorola 68(7)05, 16-b Motorola 68000, and 32-b Intel 80386 microprocessor systems. Preliminary results are encouraging and suggest that further studies of larger and more complex systems will be necessary to determine fully the benefit of the technique. The method is designed to be incorporated into a strategic selection of capability checks that collectively cover many fault classes leading to high and cost-effective reliability

Keywords

fault tolerant computing; microcontrollers; program testing; software reliability; capability checks; fault classes; invalid branches; microprocessor controllers; reliability; software-implemented fault-tolerant technique; Application software; Costs; Data analysis; Degradation; Fault detection; Fault tolerance; Fault tolerant systems; Microprocessors; Read-write memory; Software systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability and Maintainability Symposium, 1993. Proceedings., Annual

Conference_Location

Atlanta, GA

Print_ISBN

0-7803-0943-X

Type

conf

DOI

10.1109/RAMS.1993.296816

Filename

296816