Modeling and design of novel architecture of multibit switched-capacitor sigma-delta converter with two-step quantization process

This paper presents a novel architecture of high-order single-stage sigma-delta (sigma delta) converter for sensor measurement. The two-step quantization technique was utilized to design of novel architecture of sigma delta? modulator. The time steps are interleaved to achieve resolution improvement without decreasing of conversion speed. This technique can be useful for low oversampling ratio. The novel architecture was designed to obtain high dynamic range of input signal, high signal-to-noise ratio and high reliability. This paper describes steps involved in a new VHDL design of a decimation filter for a sigma delta modulator. Parameters of decimation filter are derived from the specifications of the overall sigma delta modulator. The proposed architecture of switched-capacitor (SC) sigma delta modulator was simulated with nonidealities blocks, such as sampling jitter, noise, and operational amplifier parameters (white noise, finite dc gain, finite bandwidth, slew rate and saturation voltages). The novel architecture of SC sigma delta modulator with twostep quantization process was designed and simulated in MATLAB SIMULINK.