Dynamic reconfiguration for fault tolerance for critical, real-time processor arrays

Author

Derk, M.D. ; DeBrunner, L.S.

Author_Institution

Sch. of Comput. Sci., Oklahoma Univ., Norman, OK, USA

Volume

2

fYear

1994

fDate

31 Oct-2 Nov 1994

Firstpage

1058

Abstract

Real-time digital signal processing for critical applications demands that rapid successful reconfiguration techniques be employed to increase fault tolerance. To meet this need, we introduce and demonstrate a local area reconfiguration algorithm for a rectangular processor array that is very efficient, does not require a host processor, and will successfully reconfigure for a fault anywhere in the local area if there is an available spare. Further, if all the spares in a local area are used, areas can be combined in a software controlled process, preventing a system failure

Keywords

computational complexity; distributed algorithms; fault tolerant computing; real-time systems; reconfigurable architectures; reliability; critical real-time processor arrays; dynamic reconfiguration; fault tolerance; local area reconfiguration algorithm; real-time digital signal processing; reconfiguration techniques; rectangular processor array; software controlled process; system failure; Application software; Computer science; Digital signal processing; Discrete Fourier transforms; Fault tolerance; Manufacturing processes; Matrices; Matrix decomposition; Signal processing algorithms; Speech processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 1994. 1994 Conference Record of the Twenty-Eighth Asilomar Conference on

Conference_Location

Pacific Grove, CA

ISSN

1058-6393

Print_ISBN

0-8186-6405-3

Type

conf

DOI

10.1109/ACSSC.1994.471621

Filename

471621