Integration of large-scale FPGA and DRAM in a package using chip-on-chip technology

Author

Wang, Michael X. ; Suzuki, Katsuharu ; Dai, Wayne W M ; Low, Yee L. ; O´Conner, K.J. ; Tai, King L.

Author_Institution

Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA

fYear

2000

fDate

9-9 June 2000

Firstpage

205

Lastpage

210

Abstract

A field-programmable multi-chip module containing one ORCA 3T/125 FPGA and 4 MByte DRAM was built using chip-on-chip technology. Module architecture and physical design issues are presented. A PCI board consisting of four chip-on-chip modules is also built as the test vehicle. The design environment for this multi-chip module, including visual or C++ design entry and bit-serial datapath synthesis system, is also discussed. Some ongoing approaches, like double-flip technology and area I/O are also addressed.

Keywords

DRAM chips; circuit CAD; field programmable gate arrays; flip-chip devices; integrated circuit design; integrated circuit packaging; 4 MByte; C++ design entry; DRAM; ORCA 3T/125; PCI board; bit-serial datapath synthesis; chip-on-chip technology; double-flip technology; field-programmable multi-chip module; large-scale FPGA; module architecture; physical design issues; test vehicle; CMOS logic circuits; CMOS technology; Computer architecture; Costs; Field programmable gate arrays; Large scale integration; Logic devices; Packaging; Random access memory; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific

Conference_Location

Yokohama, Japan

Print_ISBN

0-7803-5973-9

Type

conf

DOI

10.1109/ASPDAC.2000.835097

Filename

835097