Delay-optimal wiring plan for the microprocessor of high performance computing machines

Author

Kikuchi, Jun ; Sasaki, Tetsuo ; Miyamoto, Kazuhisa ; Hashimoto, Tohru

Author_Institution

Enterprise Server Div., Hitachi Ltd., Kanagawa, Japan

fYear

2000

fDate

9-9 June 2000

Firstpage

265

Lastpage

270

Abstract

This paper presents a delay-optimal designing method for high performance microprocessor. In order to develop such a microprocessor in a short period, a novel planning method for global wires, called "wiring plan" has been introduced. The goal of this wiring plan is to solve the timing issue of wires with minimum usage of wiring resources: wiring channels and inserted buffers. In this wiring plan, global assignment of wiring resources and improvement of local congestion for their usage have been performed. As a result of applying them, our chip has been able to work at 400 MHz, and channel usage has not exceeded its capacity and gate overhead for buffer insertions has been only 1.6% of total gates.

Keywords

VLSI; buffer circuits; circuit optimisation; integrated circuit design; microprocessor chips; timing; wiring; 400 MHz; buffer insertions; channel usage; delay-optimal wiring plan; gate overhead; global assignment; global wires; high performance computing machines; inserted buffers; local congestion; microprocessor; timing issue; wiring channels; wiring resources; Chip scale packaging; Delay; Feedback loop; High performance computing; Large scale integration; Logic; Microprocessors; Timing; Wires; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific

Conference_Location

Yokohama, Japan

Print_ISBN

0-7803-5973-9

Type

conf

DOI

10.1109/ASPDAC.2000.835108

Filename

835108