DocumentCode :
1890220
Title :
Thread partitioning method for hardware compiler Bach
Author :
Takahashi, Mizuki ; Ishiura, Nagisa ; Yamada, Akihisa ; Kambe, Takashi
Author_Institution :
Design Technol. Dev. Center, Sharp Corp., Nara, Japan
fYear :
2000
fDate :
9-9 June 2000
Firstpage :
303
Lastpage :
308
Abstract :
This paper presents a method for thread partitioning for a hardware compiler Bach. Bach synthesizes RT level circuits from a system description written in Bach-C language, where a system is modeled as communicating processes running in parallel. The system description is decomposed into threads, i.e., strings of sequential processes, and then converted into synthesizable behavioral VHDL models. The proposed method attempts to find a partitioning of a given system description into threads that maximize resource sharing among processes in the threads. Experiments on two real designs show that the circuit sizes were reduced by 3.7% and 14.7%. We also show the detailed statistics and analysis of the size of the resulting gate level circuits.
Keywords :
circuit CAD; high level synthesis; integrated circuit design; Bach; Bach-C language; RT level circuit synthesis; gate level circuits; hardware compiler; resource sharing; sequential processes; synthesizable behavioral VHDL models; system description; thread partitioning method; Circuit synthesis; Consumer products; Hardware; Information systems; Integer linear programming; Resource management; Statistical analysis; Synthesizers; Systems engineering and theory; Yarn;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific
Conference_Location :
Yokohama, Japan
Print_ISBN :
0-7803-5973-9
Type :
conf
DOI :
10.1109/ASPDAC.2000.835114
Filename :
835114
Link To Document :
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