DocumentCode :
1890298
Title :
TD-SCDMA system frequency synthesizer design
Author :
Lin, Wei ; Huang, Shizhen ; Tong, Gang ; Lin, Weiming
Author_Institution :
Microelectronics & Integrated Circuits of FuJian Key Laboratory Electric Department FuZhou, FuJian, P.R.China ,FuZhou University
fYear :
2008
fDate :
10-12 Nov. 2008
Firstpage :
275
Lastpage :
277
Abstract :
This paper give a design of a TD-SCDMA frequency synthesizer using multi-ring phase-locked loop, its output frequency has the very good precision and stability.The specific circuit is simulation using 0.5 um BICMOS technology and Cadence SpectreRF. The performance of whole frequency synthesizer is: its output frequency range is 2010 MHz - 2025 MHz, the frequency changing of stride is 200 KHz, the frequency locking time is smaller than 20 us, the power voltage is 3.3 V, the power consumption is 63.26 mW.
Keywords :
BiCMOS integrated circuits; code division multiple access; frequency synthesizers; phase locked loops; space division multiple access; time division multiple access; BICMOS technology; Cadence SpectreRF; TD-SCDMA frequency synthesizer; frequency 200 kHz; frequency 2010 MHz to 2025 MHz; frequency locking time; multiring phase-locked loop; power 63.26 mW; size 0.5 mum; voltage 3.3 V; Circuit simulation; Frequency conversion; Frequency synthesizers; Phase locked loops; Phase noise; RF signals; Ring oscillators; Time division synchronous code division multiple access; Voltage control; Voltage-controlled oscillators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communication Technology, 2008. ICCT 2008. 11th IEEE International Conference on
Conference_Location :
Hangzhou
Print_ISBN :
978-1-4244-2250-0
Electronic_ISBN :
978-1-4244-2251-7
Type :
conf
DOI :
10.1109/ICCT.2008.4716235
Filename :
4716235
Link To Document :
بازگشت