Analysis of power-clocked CMOS with application to the design of energy-recovery circuits

Author

Pedram, Massoud ; Wu, Xunwei

Author_Institution

Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA

fYear

2000

fDate

9-9 June 2000

Firstpage

339

Lastpage

344

Abstract

This paper presents our research results on power-clocked CMOS design. First we provide algebraic expressions and describe the properties of clocked signals. Next two types of power-clocked CMOS circuit constructions are introduced and analyzed in detail. Since the adiabatic switching requires slow-ramping of the power-clock, a clocked transmission gate and a four-stage clocked NP-domino circuit are presented which receive trapezoidal and sinusoidal power-clocks, respectively. PSPICE simulations demonstrate the correct operation and energy-saving advantage of the proposed circuits.

Keywords

CMOS logic circuits; integrated circuit design; logic design; low-power electronics; timing; PSPICE simulations; adiabatic switching; algebraic expressions; clocked signals; clocked transmission gate; energy-recovery circuit design; four-stage clocked NP-domino circuit; power-clocked CMOS; sinusoidal power-clock; trapezoidal power-clock; CMOS logic circuits; Capacitance; Clocks; Contracts; Energy conversion; Energy dissipation; Magnetic fields; Power supplies; Resistance heating; Signal analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific

Conference_Location

Yokohama, Japan

Print_ISBN

0-7803-5973-9

Type

conf

DOI

10.1109/ASPDAC.2000.835121

Filename

835121