Title :
Implementation of programmable delay lines on off-the-shelf FPGAs
Author :
Yu-Yi Chen ; Jiun-Lang Huang ; Kuo, Ted
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
The programmable delay line is a key component in test and measurement applications; it facilitates key functionalities such as de-skewing, timing adjustment, edge placement, and time-to-digital conversions. In this work, we investigate the implementation of programmable delay lines on off-the-shelf FPGAs (field programmable gate array). Two flavors of delay lines, coarse and fine, are realized and the corresponding step sizes are 105 and 13 ps, respectively.
Keywords :
circuit testing; delay lines; field programmable gate arrays; measurement systems; time-digital conversion; FPGA; deskewing functionality; edge placement; field programmable gate array; measurement application; programmable delay line; time 105 ps; time 13 ps; time-to-digital conversion; timing adjustment; Arrays; Cyclones; Delay lines; Delays; Field programmable gate arrays; Logic gates;
Conference_Titel :
AUTOTESTCON, 2013 IEEE
Conference_Location :
Schaumburg, IL
Print_ISBN :
978-1-4673-5681-7
DOI :
10.1109/AUTEST.2013.6645040
