DocumentCode :
1890669
Title :
A system design for UHF RFID reader
Author :
Ying, Chen ; Fu-Hong, Zhang
Author_Institution :
Coll. of Commun., Hangzhou Dianzi Univ., Hangzhou
fYear :
2008
fDate :
10-12 Nov. 2008
Firstpage :
301
Lastpage :
304
Abstract :
This paper introduces a system design for RFID reader. The RFID reader is compatible with EPC Class-1, Generation-2 Standard, operating at the 915 MHz band. The UHF RFID reader includes RF analog front end (AFE), the base band design and clock control. The RFID RF AFE contains transmitting circuit, receiving circuit, frequency synthesize, circulator, etc. The base band contains the FPGA chip, 100 M hardware resources of network supporting, DDR SDRAM, FLASH, A/D, D/A, etc. The FPGA chip inseted NiosII soft core. This architecture is an advantage for implementing various kinds of RFID standards by changing the soft of NiosII core in FPGA, and efficiently reduces the design and development time and cost.
Keywords :
UHF circuits; data acquisition; radiofrequency identification; EPC class-1 generation-2 Standard; FPGA chip; NiosII soft core; RF analog front end; UHF RFID reader; base band design; clock control; frequency 915 MHz; Circuit synthesis; Clocks; Control system synthesis; DRAM chips; Field programmable gate arrays; Frequency synthesizers; Hardware; Network synthesis; Radio frequency; Radiofrequency identification; Nios II; RF AFE; RFID reader; base band;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communication Technology, 2008. ICCT 2008. 11th IEEE International Conference on
Conference_Location :
Hangzhou
Print_ISBN :
978-1-4244-2250-0
Electronic_ISBN :
978-1-4244-2251-7
Type :
conf
DOI :
10.1109/ICCT.2008.4716249
Filename :
4716249
Link To Document :
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