DocumentCode
1890714
Title
The implementation of POWER7TM: A highly parallel and scalable multi-core high-end server processor
Author
Wendel, Dieter ; Kalla, R. ; Cargoni, R. ; Clables, J. ; Friedrich, J. ; Frech, R. ; Kahle, J. ; Sinharoy, B. ; Starke, William ; Taylor, Stephen ; Weitzel, S. ; Chu, S.G. ; Islam, Shariful ; Zyuban, V.
Author_Institution
IBM, Boeblingen, Germany
fYear
2010
fDate
7-11 Feb. 2010
Firstpage
102
Lastpage
103
Abstract
POWER7TM the next generation processor of the POWERTM family is introduced. The 8-core chip, supporting 32 threads, is implemented in 45 nm 11 M CMOS SOI. The 32 kB L1 caches feature 1 read port banked write for the l-cache and 2 read ports banked write for the Dcache. The on-chip cache hierarchy consists of a 256 kB fast, private SRAM L2 and a 32MB shared L3, implemented in embedded DRAM.
Keywords
DRAM chips; SRAM chips; cache storage; microprocessor chips; multiprocessing systems; parallel architectures; 8-core chip; CMOS SOI; DRAM; Dcache; POWER7; memory size 256 KByte; memory size 32 KByte; memory size 32 MByte; on-chip cache hierarchy; parallel server processor; private SRAM L2; read port banked write; scalable multicore high end server processor; shared L3; size 45 nm; CMOS technology; Capacitors; Clocks; Delay; Energy consumption; Frequency domain analysis; Logic; Random access memory; Voltage; Yarn;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
978-1-4244-6033-5
Type
conf
DOI
10.1109/ISSCC.2010.5434074
Filename
5434074
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