Title :
A wire-speed powerTM processor: 2.3GHz 45nm SOI with 16 cores and 64 threads
Author :
Johnson, Chris ; Allen, D.H. ; Brown, Jason ; VanderWiel, S. ; Hoover, Randy ; Achilles, H. ; Cher, Chen-Yong ; May, G.A. ; Franke, Hubertus ; Xenedis, J. ; Basso, Claude
Author_Institution :
IBM Res., Rochester, MN, USA
Abstract :
A 64-thread simultaneous multi-threaded processor uses architecture and implementation techniques to achieve high throughput at low power. Included are static VDD scaling, multi-voltage design, clock gating, multiple VDD devices, dynamic thermal control, eDRAM and low voltage circuit design. Power is reduced by >50% in a 428 mm2 chip. Worst-case power is 65 W at 2.0 GHz, 0.85 V.
Keywords :
microprocessor chips; multi-threading; silicon-on-insulator; SOI; clock gating; dynamic thermal control; eDRAM; frequency 2 GHz; frequency 2.3 GHz; low voltage circuit design; multithreaded processor; multivoltage design; power 65 W; silicon on insulator; size 45 nm; voltage 0.85 V; wire speed power processor; Capacitance; Circuits; Clocks; Latches; Logic devices; Logic programming; Noise reduction; Random access memory; Temperature; Timing;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-6033-5
DOI :
10.1109/ISSCC.2010.5434075
