• DocumentCode
    1890766
  • Title

    An x86-64 core implemented in 32nm SOI CMOS

  • Author

    Jotwani, Ravi ; Sundaram, Suresh ; Kosonocky, Stephen ; Schaefer, Anna ; Andrade, Valeria ; Constant, G. ; Novak, A. ; Naffziger, Samuel

  • Author_Institution
    AMD, Austin, TX, USA
  • fYear
    2010
  • fDate
    7-11 Feb. 2010
  • Firstpage
    106
  • Lastpage
    107
  • Abstract
    The 32 nm implementation of an AMD x86-64 core occupying 9.69 mm2 and containing more than 35 million transistors (excluding L2 cache), operates at frequencies >3 GHz. The core incorporates numerous design and power improvements to enable an operating range of 2.5 to 25 W and a zero-power gated state that make the core well-suited to a broad range of mobile and desktop products.
  • Keywords
    CMOS digital integrated circuits; microcomputers; microprocessor chips; mobile computing; AMD microprocessor; SOI CMOS; desktop products; mobile applications; power 2.5 W to 25 W; size 32 nm; zero power gated state; Circuits; Clocks; Delay; Design optimization; Frequency; MOS devices; Monitoring; Timing; Variable structure systems; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    978-1-4244-6033-5
  • Type

    conf

  • DOI
    10.1109/ISSCC.2010.5434076
  • Filename
    5434076
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1890766