Optimization of V/sub DD/ and V/sub TH/ for low-power and high-speed applications

Author

Nose, Koichi ; Sakurai, Takayasu

Author_Institution

Inst. of Ind. Sci., Tokyo Univ., Japan

fYear

2000

fDate

9-9 June 2000

Firstpage

469

Lastpage

474

Abstract

Closed-form formulas are presented for optimum supply voltage (V/sub DD/) and threshold voltage (V/sub TH/) that minimize power dissipation when technology parameters and required speed are given. The formulas take into account short-channel effects and the variation of V/sub TH/ and temperature. Using typical device parameters, it is shown that a simple guideline to optimize the power consumption is to set the ratio of maximum leakage power to total power about 30%. Extending the analysis, the future VLSI design trend is discussed. The optimum V/sub DD/ coincides with the SIA roadmap and the optimum V/sub TH/ for logic blocks at the highest temperature and at the lowest process variation corner is in the range of 0 V-0.1 V over generations.

Keywords

VLSI; circuit optimisation; high-speed integrated circuits; integrated circuit design; low-power electronics; VLSI; low-power high-speed design; optimization; power dissipation; short channel effect; supply voltage; threshold voltage; Circuits; Constraint optimization; Delay; Energy consumption; Fluctuations; Nose; Power dissipation; Temperature; Threshold voltage; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific

Conference_Location

Yokohama, Japan

Print_ISBN

0-7803-5973-9

Type

conf

DOI

10.1109/ASPDAC.2000.835145

Filename

835145