DocumentCode :
1891052
Title :
A 3D IC designs partitioning algorithm with power consideration
Author :
Chang, Ho-Lin ; Lai, Hsiang-Cheng ; Hsueh, Tsu-Yun ; Cheng, Wei-Kai ; Chi, Mely Chen
Author_Institution :
Dept. of Inf. & Comput. Eng., Chung Yuan Christian Univ., Chungli, Taiwan
fYear :
2012
fDate :
19-21 March 2012
Firstpage :
137
Lastpage :
142
Abstract :
We present an effective algorithm to partition a circuit into k layers under power density constraints for 3D IC designs. Our algorithm utilizes a multilevel structure and a successive 3D aware two-way partition method to minimize the number of signal TS Vs and area overhead. A layer swapping technique is used to improve total number of signal TSVs and power TSVs. Finally, a zero-gain cell move technique is used to refine the area overhead. Our test cases are 4 industrial circuits provided in the IC/CAD 2011 contest in Taiwan [1]. Experimental results show that our results are better than those of all teams in the contest. In addition, we study the impact on signal TSVs of an extended hMetics method, simultaneous k-way partition, and successive two-way partition for k layer 3D ICs. The results show that the successive two-way partition method is superior to the other methods both in number of TSVs and run time.
Keywords :
integrated circuit design; power integrated circuits; three-dimensional integrated circuits; 3D IC designs partitioning algorithm; 3D aware two-way partition method; area overhead; extended hMetics method; industrial circuits; layer swapping technique; multilevel structure; power TSV; power consideration; power density constraints; signal TSV; simultaneous k-way partition; successive two-way partition; zero-gain cell move technique; Benchmark testing; Logic gates; Mathematical model; Partitioning algorithms; Three dimensional displays; Through-silicon vias; 3D IC; Multilevel multilayer partitioning; Power density constraint; Three dimensional integrated circuit partition; Through Silicon Via (TSV);
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality Electronic Design (ISQED), 2012 13th International Symposium on
Conference_Location :
Santa Clara, CA
ISSN :
1948-3287
Print_ISBN :
978-1-4673-1034-5
Type :
conf
DOI :
10.1109/ISQED.2012.6187486
Filename :
6187486
Link To Document :
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