Title :
Fault models and test generation for IDDQ testing
Author :
Higami, Yoshinobu ; Takamatsu, Yuzo ; Saluja, Kewal K. ; Konshita, K.
Author_Institution :
Ehime Univ., Matsuyama, Japan
Abstract :
This paper surveys recent research related to IDDQ testing, particularly focusing on fault models and test generation methods. (1) The paper provides a taxonomy of fault models that have been studied in literature, and classifies these models into a small set of faults. (2) The paper describes efficient test generation methods and fault simulation methods. Test compaction methods, including reduction of the total number of test vectors and selection of IDDQ measurement vectors, are also described.
Keywords :
CMOS digital integrated circuits; fault simulation; integrated circuit modelling; integrated circuit testing; logic testing; CMOS; IDDQ testing; fault models; fault simulation methods; logic testing; taxonomy; test compaction methods; test generation; test vectors; Circuit faults; Circuit testing; Compaction; Current measurement; Electrical fault detection; Electronic equipment testing; Fault detection; Fluid flow measurement; Logic testing; Taxonomy;
Conference_Titel :
Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific
Conference_Location :
Yokohama, Japan
Print_ISBN :
0-7803-5973-9
DOI :
10.1109/ASPDAC.2000.835152
