Embedded tutorial: issues on SOC testing in DSM era

Summary form only given, as follows. Deep sub-micron technology is rapidly leading to exceedingly complex, billion-transistor chips. By these technology evolutions, a system is integrated into a chip, the so-called system-on-a-chip (SOC). In order to bridge the gap between available transistors and design in SOC, higher-level behavioral language and re-use of already designed intellectual property (IP) will become more common. However, these techniques affect test methodologies and failure analysis of SOC. On the other hand, SOCs are implemented as a collection of heterogeneous circuits such as ASICs, DRAMs and analog circuits, so there will be large impact on Design for Testability techniques (DFT) and test cost issues. New test methods involving built-in-self-test (BIST) are required that will allow low-speed, low-cost automatic test equipment (ATE) to test the digital portions of SOCs at high speed. In the aspect of test quality, new fault models will be required to handle crosstalk and new failure modes that will result from multi-level metal structures. The old "stuck-at" single fault model is becoming less effective for computing expected test results for complex SOC.