An extended-range incremental CT ∑Δ ADC with optimized digital filter

Extended range approach has been employed in discrete-time incremental sigma-delta analog-to-digital converters to reduce the number of cycles per conversion and therefore the power dissipation. In this work, extended range is combined with continuous-time filter implementation so as to reduce the integrators gain-bandwidth product requirement. The proposed architecture and mathematical analysis are presented using a 3^rd order single-loop single-bit sigma-delta modulator as proof-of-concept. In order to overcome the analog-digital transfer functions mismatches, an appropriate digital filter is designed using optimization tools. Behavioral simulations show that the proposed architecture with an optimized filter achieves 13.8 bits resolution with a 4 k Samples/sec sampling rate to comply with a high-resolution biomedical application.