DocumentCode
1891289
Title
A low drift programmable video clock synthesiser
Author
Lahuec, Cyril ; Horan, John ; Duigan, Joe
Author_Institution
Cork Inst. of Technol., Ireland
fYear
2002
fDate
2002
Firstpage
121
Lastpage
125
Abstract
This paper presents a video clock synthesiser. The block is programmable, it accepts input frequencies from 20 kHz to 5 MHz and produces output frequencies up to 200 MHz. The rms jitter is 20 ps and the phase drift is less than 0.5 ns which represents an improvement by a factor of 6 on Begueret et al. (2001). The device VDD sensitivity is 0.18%/V, this makes it suitable for integration in noisy ASICs. The area is 1.2 mm2 in 0.25 μm CMOS and it consumes 17 mW at 110 MHz.
Keywords
CMOS analogue integrated circuits; VHF circuits; clocks; delay lock loops; frequency synthesizers; integrated circuit layout; network topology; programmable circuits; video signals; 0.25 micron; 110 MHz; 17 mW; CMOS; analogue IC; device VDD sensitivity; input frequencies; low drift programmable video clock synthesiser; output frequencies; phase drift; rms jitter; CMOS process; Clocks; Delay lines; Jitter; Noise generators; Phase locked loops; Phase noise; Ring oscillators; Testing; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrotechnical Conference, 2002. MELECON 2002. 11th Mediterranean
Print_ISBN
0-7803-7527-0
Type
conf
DOI
10.1109/MELECON.2002.1014543
Filename
1014543
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