• DocumentCode
    1891345
  • Title

    On lithography aware metal-fill insertion

  • Author

    Suresh, Vikram B. ; Kumar, P.V. ; Kundu, Sandip

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Massachusetts, Amherst, MA, USA
  • fYear
    2012
  • fDate
    19-21 March 2012
  • Firstpage
    200
  • Lastpage
    207
  • Abstract
    Manufacturability and lithographic printability are growing concerns with advancing technology nodes. The two most important parameters which influence the printability of a design are lithographic process corner and pattern density of the design. Dummy metal-fills are used to improve post-chemical mechanical polishing surface planarity. Conventional metal-fills do not consider impact of fill on lithographic printability or critical area-this is the focus of our paper. Although systematic yield due to lithographic distortions is gaining prominence, paniculate defects still remain a significant source of yield loss. Increasing design density in conjunction with growing manufacturability issues necessitates lithography aware paniculate limited yield loss analysis. In this work, we propose a novel lithography aware metal-fill insertion technique taking both statistical lithographic variations and critical area into consideration. Specifically, the main contributions of this work are a) analyzing the influence of metal-fills on line width variation and critical area, b) synthesis of variational lithography-aware metal-fill to improve design yield. The solution is been built on existing commercial tools. Experiments on ISCAS´85 benchmark circuits reveal that in 45nm technology, metal-fills worsen the linewidth variation by as much as 15% for more than 30% of nets compared to no fill. By contrast, proposed lithography aware metal-fill reduces linewidth variation by -25% and critical area by -35% compared to conventional metal-fill solutions without sacrificing density, planarity and performance targets.
  • Keywords
    filler metals; lithography; lithographic distortions; lithographic printability; lithography aware metal-fill insertion; manufacturability; post-chemical mechanical polishing surface planarity; statistical lithography; Benchmark testing; Integrated circuit interconnections; Layout; Lithography; Metals; Routing; Timing; Critical Area; Linewidth variation; Lithography; Metal-fill;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality Electronic Design (ISQED), 2012 13th International Symposium on
  • Conference_Location
    Santa Clara, CA
  • ISSN
    1948-3287
  • Print_ISBN
    978-1-4673-1034-5
  • Type

    conf

  • DOI
    10.1109/ISQED.2012.6187495
  • Filename
    6187495