Title :
A method for linking process-level variability to system performances
Author :
Fujita, Tomohiro ; Okada, Ken-ichi ; Fujita, Hiroaki ; Onodera, Hidetoshi ; Tamaru, Keikichi
Author_Institution :
Dept. of Commun. & Comput. Eng., Kyoto Univ., Japan
Abstract :
In this paper we present a statistical analysis method which bridges the statistical information between process-level and system-level. This enables us to evaluate the effect of process variation at the system level. Also, we can derive constraints on the process variation from a performance requirement. We show an example of the hierarchical statistical analysis applied to a Phase Locked Loop (PLL) circuit.
Keywords :
VLSI; analogue integrated circuits; integrated circuit modelling; phase locked loops; statistical analysis; PLL circuit; analog VLSI circuits; hierarchical statistical analysis; phase locked loop circuit; process variation constraints; process-level variability; statistical analysis method; system performances; Analytical models; Bridge circuits; Circuit simulation; Informatics; Joining processes; Performance analysis; Response surface methodology; Statistical analysis; System performance; Very large scale integration;
Conference_Titel :
Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific
Conference_Location :
Yokohama, Japan
Print_ISBN :
0-7803-5973-9
DOI :
10.1109/ASPDAC.2000.835161
