The design of a multi-chip single package digital signal processing module

A 32-b floating-point digital signal processor IC is integrated with eight 16 K×4-b SRAM chips on a silicon substrate, thus minimizing the parasitic loading to the processor buffer and enabling zero-wait-state access of the full 64-kB of memory. The module is rated at 25 MHz up to 125°C and 70 MHz at liquid nitrogen temperature. A large percentage of modules operate up to 40 MHz at room temperature. The assembly is packaged in a standard 133 pin PGA ceramic package identical in size and footprint with the package used for the signal processor IC alone. This multichip packaging approach has significant potential for improving system performance and reducing cost. The signal processing module described was designed as a vehicle for such demonstration. The electrical analysis and design criteria, physical packaging, and testing strategies are discussed