Interconnect analysis in spin-torque devices: Performance modeling, sptimal repeater insertion, and circuit-size limits

A spin-torque device may be considered as the basic building block of an information processing system utilizing electron spin as the state variable. In this paper, interconnection aspects of spin-torque circuits are analyzed and their performance and energy dissipation are compared against those of their conventional electrical counterparts at the 7.5nm technology node. Spin circuits with two flavors of nanomagnet dynamics are considered: (a) nanomagnets with complete spin-torque assisted switching and (b) nanomagnets with mixed-mode switching utilizing Bennett clocking. The interconnect in the spin-torque logic is assumed to be implemented with graphene nanoribbons. It is found that a spin system with a full spin-torque assisted switching may have energy dissipation equal to that of the CMOS system only if electrical currents as low as 250nA are utilized with half-metal ferromagnet electrodes. To account for the spin signal loss within the interconnect, spin repeaters must be inserted along the interconnect. It is found that the optimal repeater insertion frequency to minimize the delay of the spin system is 2-3× higher than the critical repeater insertion frequency (to compensate only for signal losses.) Using Rent´s rule-based interconnect density function in a random logic block, a comparison of the average performance and energy dissipation of spin and CMOS circuits as a function of circuit size and complexity is provided. The upper bound on the size of the spin circuit in the presence of spin repeaters is also quantified.