A new low-power, low-area, parallel prefix Sklansky adder with reduced inter-stage connections complexity

In this paper a relation between graph energy and electrical energy or power consumption with graph nodes and edges for PPA structures is introduced. The Sklansky PPA is selected as the target PPA and its recursion steps limited. This reduced the internal nodes of the PPA. The reduction of nodes and edges and limiting the recursive stages to maximum 8 steps, resulted in proposed adder I and using special dot and semi-dot operators for graph nodes in proposed adder I led to proposed adder II. The number of transistors, total power and critical delay path of our proposed adder II are reduced about 31%, 29% and 7% versus Sklansky adder respectively. Finally the power-delay-product (PDP) of proposed PPA II comes with about 35% improvement compared with Sklansky adder.