Robust metastability-based TRNG design in nanometer CMOS with sub-vdd pre-charge and hybrid self-calibration

In this work, we study the impact of sub-vdd pre-charge operation of metastability-based True Random Number Generator (TRNG) and propose a hybrid self-calibration to improve the statistics of the TRNG in the presence increasing intra-die variation. Circuits designed in deep submicron technologies are susceptible to process variation. The variability may affect the circuit performance, power and reliability. Numerous pre-silicon design methodologies and post-silicon circuit tuning mechanisms have been studied in literature. We propose a sub-vdd pre-charge technique to improve the tolerance of the TRNG to device mismatch. This is followed by a hybrid self-detection and calibration technique based on algorithmic post processing and circuit tuning to mitigate the effects of variability. The cryptographic metric of `bit entropy´ is used to validate the proposed techniques. The TRNG circuit and the proposed techniques are implemented using 45nm PDK. Results show that variation in fabrication process affect the reliability of TRNG circuits. Pre-charging the TRNG to 0.7V for a typical supply voltage of 1.1V reduces the impact of device mismatch on the circuit by 2X for device mismatch as large as 4-5%. The hybrid self-calibration further improves the bit entropy by ~120% across a range of 5% intra-die variation. The simple control logic has an estimated area of 128 um² and results in a negligible energy overhead of 0.82 fJ/bit.