A 12b 50 MHz 3.3 V CMOS acquisition time minimized A/D converter

A 126 50 MHz CMOS analog-to-digital converter (ADC) based on a pipelined architecture was designed to demonstrate acquisition time minimization techniques for high-speed two-stage amplifiers. The proposed techniques reduce overshoots and undershoots of amplifier outputs and acquisition time by controlling the bias currents of amplifiers. The prototype ADC was fabricated in a 0.35 um double-poly triple-metal n-well CMOS technology. The measured signal-to-noise-and-distortion ratio is improved by more than 5 dB using the proposed techniques at a 50 MHz clock. The ADC power consumption is 200 mW at 3.3 V and 50 MHz.