DocumentCode
1891782
Title
5/spl times/4 Gbps 0.35 micron CMOS CRC generator designed with standard cells
Author
Serrano, José Maria Nadal
Author_Institution
ETSI Telecomunicacion, Tech. Univ. of Madrid, Spain
fYear
2002
fDate
9-9 May 2002
Firstpage
215
Lastpage
219
Abstract
Design highlights for a 32-bit parallel and highly pipelined cyclic redundancy code (CRC) generator are presented. The design can handle 5 different channels at an input rate of 2 Gbps each (the total output throughput is 5×4 Gbps.) The generated CRCs are compatible with the 32-bit Ethernet standards. The circuit has been implemented with standard cells in a 0.35μm standard CMOS process using the properties of Galois fields and has been conceived as a "free" IP.
Keywords
CMOS logic circuits; Galois fields; error detection; integrated circuit design; 0.35 micron; 2 Gbit/s; 32 bit; 5 Gbit/s; CMOS process; Ethernet standards; Galois fields; cyclic redundancy code generator; digital IC design; free IP; layout oriented VHDL description; parallel CRC generator; pipelined CRC generator; standard cells; two-phase logic; CMOS process; Circuits; Code standards; Cyclic redundancy check; Electronic mail; Ethernet networks; Galois fields; Polynomials; Telecommunication standards; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrotechnical Conference, 2002. MELECON 2002. 11th Mediterranean
Conference_Location
Cairo, Egypt
Print_ISBN
0-7803-7527-0
Type
conf
DOI
10.1109/MELECON.2002.1014561
Filename
1014561
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