Title :
Design of an integrated CMOS PLL frequency synthesizer
Author_Institution :
Carl & Emily Fuchs Inst. for Microelectron., Pretoria Univ.
Abstract :
Due to higher costs, bulkiness and larger power consumption, it is no longer desirable to implement wireless transceivers with discrete elements. This paper describes the design of an essential component in wireless transceivers, the frequency synthesizer. The synthesizer is implemented using the dual phase locked loop (PLL) architecture. The synthesizer generates signals in the 2.4-2.5 GHz range with a 1 MHz resolution. Using the 0.35 μm CMOS process, post-layout simulations showed a phase noise of -82 dBc/Hz at an offset of 10 kHz and reference sidebands at -60 dBc, both these parameters with respect to a 2.45 GHz carrier.
Keywords :
CMOS integrated circuits; circuit simulation; frequency synthesizers; integrated circuit layout; integrated circuit modelling; phase locked loops; phase noise; signal resolution; transceivers; 0.35 micron; 2.4 to 2.5 GHz; 2.45 GHz; CMOS PLL frequency synthesizer design; CMOS process; SSB mixer; VCO; carrier frequency; discrete elements; dual PLL architecture; dual phase locked loop architecture; frequency offset; frequency synthesizer; on-chip inductor; phase noise; post-layout simulations; power consumption; reference sidebands; signal range; signal resolution; single sideband mixer; wireless transceivers; CMOS process; CMOS technology; Frequency synthesizers; Phase locked loops; Phase noise; Signal generators; Signal resolution; Transceivers; Voltage-controlled oscillators; Wireless communication;
Conference_Titel :
Electrotechnical Conference, 2002. MELECON 2002. 11th Mediterranean
Print_ISBN :
0-7803-7527-0
DOI :
10.1109/MELECON.2002.1014562
