Importance of CAD tools and methodologies in high speed CPU design

Author

Tago, Haruyuki ; Hashimoto, Kazuhiro ; Ikumi, Nobuyuki ; Nagamatsu, Masato ; Suzuoki, Masakazu ; Yamamoto, Yasuyuki

Author_Institution

Semicond. Co., Toshiba Corp., Kawasaki, Japan

fYear

2000

fDate

9-9 June 2000

Firstpage

631

Lastpage

633

Abstract

Design methodologies and CAD for "Emotion Engine" LSI are presented with emphasis on practical aspects of verification and timing closure. A combination of simulation, emulation and formal verification ensured the functional first silicon for system evaluation. In order to control wire delay in early design stage, floor plan based synthesis and wire load estimation are adopted for quick timing closure.

Keywords

circuit layout CAD; embedded systems; formal verification; high level synthesis; logic partitioning; microprocessor chips; reduced instruction set computing; software tools; timing; CAD tools; Emotion Engine LSI; clock skew management; design methodologies; emulation; floor plan based synthesis; formal verification; functional first silicon; high speed CPU design; image processing unit; memory controller; repeater insertion; simulation; superscalar RISC core; system evaluation; timing closure; vector units; wire delay; wire load estimation; Control system synthesis; Delay estimation; Design automation; Design methodology; Emulation; Formal verification; Large scale integration; Silicon; Timing; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific

Conference_Location

Yokohama, Japan

Print_ISBN

0-7803-5973-9

Type

conf

DOI

10.1109/ASPDAC.2000.835176

Filename

835176