Title :
Repeater insertion method and its application to a 300 MHz 128-bit 2-way superscalar microprocessor
Author :
Kojima, Norman ; Paramwswar, Y. ; Klingner, Christian ; Ohtaguro, Y. ; Matsui, Masataka ; Iwasa, Shigeaki ; Teruyama, Tatsuo ; Shimazawa, Takayoshi ; Takeda, Hideki ; Hashizume, Kouji ; Tago, Haruyuki ; Yamada, Masaaki
Author_Institution :
Design Methodology Dept., Toshiba Corp. Semicond. Co., Kawasaki, Japan
Abstract :
Interconnect delay is dominant in today\´s high speed VLSI circuits and there have been various studies on ways to resolve it. A repeater insertion tool "RePertory" has been developed to solve the interconnect timing problem on a 300 MHz 128-bit 2-way superscalar microprocessor. Because of its practical simple algorithm, the location of over 5700 repeaters distributed over 5 modules is calculated in 26 minutes on 5 UltraSPARC-II 360 MHz in parallel. This paper describes the goals of RePertory for this project, the timing improvement flow with RePertory, the results and analysis of this repeater insertion method.
Keywords :
VLSI; circuit layout CAD; high level synthesis; integrated circuit interconnections; logic partitioning; microprocessor chips; reduced instruction set computing; timing; vector processor systems; 128 bit; 2-way superscalar microprocessor; 300 MHz; Emotion Engine; RISC core; RePertory tool; VLSI; design flow; electromigration violations; floor plan; interconnect timing problem; module boundaries preservation; next generation video console; repeater insertion method; vector processing unit; Automatic control; Delay; Electromigration; Engines; Integrated circuit interconnections; Large scale integration; Microprocessors; Repeaters; Timing; Very large scale integration;
Conference_Titel :
Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific
Conference_Location :
Yokohama, Japan
Print_ISBN :
0-7803-5973-9
DOI :
10.1109/ASPDAC.2000.835178
