Clock design of 300 MHz 128-bit 2-way superscalar microprocessor

Author

Ishihara, Fujio ; Klingner, Christian ; Agawa, Ken-ichi

Author_Institution

Processor Dev. Group, Toshiba Corp., Kawasaki, Japan

fYear

2000

fDate

9-9 June 2000

Firstpage

647

Lastpage

652

Abstract

Less than 116 ps overall clock skew has been achieved across the 15.02 mm/spl times/15.03 mm die by balanced clock path routing and differential clock signal distribution in the global clock tree of 300 MHz 128-bit 2-way superscalar microprocessor. The shared clock wire configuration and clock buffer layout patterns over the whole die enhance the clock skew insensitivity to process fluctuation. A combination of three different clock tuning methods is successfully applied to the entire clock tree and the clock skew is minimized efficiently within a limited design period.

Keywords

VLSI; circuit layout CAD; circuit tuning; logic partitioning; microprocessor chips; parallel architectures; reduced instruction set computing; timing; 128 bit; 2-way superscalar microprocessor; 300 MHz; balanced clock path routing; buffer outputs; clock buffer layout patterns; clock design; clock skew; clock tuning methods; differential clock signal distribution; global clock tree; global tree; process fluctuation; shared clock wire configuration; Circuit optimization; Clocks; Fluctuations; Integrated circuit interconnections; Microelectronics; Microprocessors; Phase locked loops; Routing; Ultra large scale integration; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific

Conference_Location

Yokohama, Japan

Print_ISBN

0-7803-5973-9

Type

conf

DOI

10.1109/ASPDAC.2000.835179

Filename

835179