Title :
Half-micron gate GaAs MESFET technology using selectively-grown N/sup +/ layer for high speed static RAM fabrication
Author :
Matsunaga, N. ; Miyazaki, M. ; Kagaya, O. ; Haga, T. ; Tanaka, H. ; Yanazawa, H.
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
Processing technology for a high-performance 0.5- mu m gate GaAs MESFET using a selectively grown n/sup +/ layer is described. In order to realize the high-performance MESFET with a 0.5- mu m gate, a selectively grown n/sup +/ layer and a shallow MESFET channel were used. The low-resistivity n/sup +/ layer markedly decreases the series resistance of the MESFET and realizes a high K value of more than 500 mS/Vmm. However, in order to utilize the process in LSI fabrication, the problem of the dependence of growth rate on the pattern density must be overcome. In this study, dummy pattern is added to the low-density region to get uniform growth rate of the SRAM (static RAM) chip. The technology has been used to realize a 4-kb SRAM with subnanosecond access time.<>
Keywords :
III-V semiconductors; Schottky gate field effect transistors; field effect integrated circuits; gallium arsenide; integrated circuit technology; integrated memory circuits; large scale integration; random-access storage; 0.5 micron; 4 kbit; GaAs; GaAs MESFET technology; LSI fabrication; SRAM; dummy pattern; growth rate; high K value; high speed static RAM; low-density region; pattern density; selectively-grown N/sup +/ layer; semiconductors; shallow MESFET channel; submicron; subnanosecond access time; uniform growth rate; Electrodes; Fabrication; Gallium arsenide; Ion implantation; Large scale integration; MESFETs; MOCVD; Read-write memory; Substrates; Threshold voltage;
Conference_Titel :
Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1989. Technical Digest 1989., 11th Annual
Conference_Location :
San Diego, CA, USA
DOI :
10.1109/GAAS.1989.69314
