Conversion of two- to four-phase delay-insensitive asynchronous circuits

Asynchronous logic design has gained more and more interest over last few years. However, as many designers are well aware, there exist various different and relatively diverse asynchronous design methodologies. In order to obtain a highly optimized and efficient circuit implementation, it is often necessary to mix various methodologies for exploiting their specific benefits. Consequently, the need for efficient protocol conversion interfaces between these different techniques arises. In this paper we take a look on how such conversion blocks can be built efficiently, especially with respect to area consumption. By thoroughly analyzing the properties of the used protocols we elaborate the necessary requirements for an exemplary two-phase to four-phase converter, and present the respective circuit in combination with simulation results. The methodology can easily be extended for other protocol conversions.