• DocumentCode
    1892514
  • Title

    Silicon technology directions in the nanoelectronics era

  • Author

    Pinto, Mark R.

  • Author_Institution
    Appl. Mater., Santa Clara, CA, USA
  • fYear
    2005
  • fDate
    9-11 May 2005
  • Abstract
    For decades the scalability of MOS technology has fostered continual improvements in almost every dimension of electronic products. However at ∼130nm, VLSI has neared a variety of limits threatening compromises, and the industry has returned to a state more like the 1970s where new directions in materials, processes and devices are being intensively evaluated. However the complexity of the challenge today is many orders of magnitude higher - e.g. controlling atomic thickness over billions of components - while economic pressures, both on R&D as well as time to yield, are driving a new industry landscape. This presentation explores key technology challenges and reviews main industry directions - many times across traditional R&D boundaries - that enables the pervasive growth in application content promised by the nanoelectronics era.
  • Keywords
    CMOS integrated circuits; VLSI; nanoelectronics; research and development; MOS technology; VLSI; electronic products; industry directions; nanoelectronics era; silicon technology; technology challenges; time to yield; Costs; Lithography; Nanoelectronics; Optical films; Pressure control; Product design; Research and development; Scalability; Silicon; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Integrated Circuit Design and Technology, 2005. ICICDT 2005. 2005 International Conference on
  • Print_ISBN
    0-7803-9081-4
  • Type

    conf

  • DOI
    10.1109/ICICDT.2005.1502574
  • Filename
    1502574