DocumentCode
1892571
Title
A dynamic clock skew compensation circuit technique for low power clock distribution
Author
Yamashita, Takahiro ; Fujimoto, Tetsuya ; Ishibashi, Koichiro
Author_Institution
Semicond. Technol. Acad. Res. Center, Yokohama, Japan
fYear
2005
fDate
9-11 May 2005
Firstpage
7
Lastpage
10
Abstract
Clock tree synthesis (CTS) is an essential technique for SoC design. A dynamic skew compensation technique is proposed here, which relaxes the CTS requirements and contributes to both small skew and low power operation. A test chip has been fabricated using 0.13-μm CMOS technology. Measured results show a 44% skew improvement from a 100-ps initial skew. This technique can be easily implemented in the current CTS flow.
Keywords
CMOS digital integrated circuits; clocks; delay circuits; integrated circuit design; low-power electronics; system-on-chip; timing circuits; timing jitter; 0.13 micron; CMOS technology; clock tree synthesis; dynamic clock skew compensation circuit; dynamic skew compensation; low power clock distribution; system-on-chip; Circuits; Clocks; Delay; Detectors; Flip-flops; MOSFETs; Phase detection; Voltage; Wire; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Circuit Design and Technology, 2005. ICICDT 2005. 2005 International Conference on
Print_ISBN
0-7803-9081-4
Type
conf
DOI
10.1109/ICICDT.2005.1502576
Filename
1502576
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