Title :
Cost-minimized double die DRAM packaging for ultra-high performance DDR3 and DDR4 multi-rank server DIMMs
Author :
Crisp, Richard ; Gervasi, Bill ; Zohni, Wael ; Haba, Bel
Author_Institution :
Invensas Corp., San Jose, CA, USA
Abstract :
A cost-minimized generation-spanning double die DRAM packaging (DDP) technology suitable for making ultra-high performance high-capacity server DIMMs for both the DDR3 and DDR4 DRAM generations was developed. Using existing wirebond-based manufacturing infrastructure it is immediately deployable with no new assembly equipment required. Significant results were obtained relating to performance enhancement and cost reduction versus existing packaging and DIMM designs. Both die are mounted face down in the package with each showing identical performance. Bin split yields are enhanced significantly. The package bailout features placement of the command and address terminals in the center of the package permitting single-layer routing of the timing-critical address and command bus at the DIMM level. Data and Data Strobe signals have shorter routing stubs on the DIMM. The improved PCB layout resulting from the new bailout resulted in a quadrank RDIMM capable of operating at over 1600MT/s in a two DIMM per channel configuration: 50% faster than standard DIMMs. The face-down laterally displaced die arrangement with a sub-1mm package thickness reduces the thermal impedance by 25% versus conventional DDPs. Total assembly cost is the lowest of any DDP and on a per-die basis is lower than Single Die Packaging.
Keywords :
DRAM chips; lead bonding; network routing; printed circuit layout; DDR3 DRAM generations; DDR4 multi-rank server; DIMM; PCB layout; command bus; cost reduction; displaced die arrangement; generation spanning double die DRAM packaging; package bailout; package thickness; performance enhancement; single die packaging; single layer routing; thermal impedance; timing-critical address; total assembly cost; wirebond-based manufacturing infrastructure; Assembly; Face; Impedance; Packaging; Random access memory; Routing; Substrates; DDP; DDR3; DDR4; Hypercloud; LRDIMM; RDIMM; RDL; wirebond;
Conference_Titel :
Quality Electronic Design (ISQED), 2012 13th International Symposium on
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4673-1034-5
DOI :
10.1109/ISQED.2012.6187546