A yield-aware modeling methodology for nano-scaled SRAM designs

In this paper, a modeling methodology to maximize the yield of a SRAM memory array is presented. The method is robust to process variations. Calibrated models for the distributions of performance parameters are used to predict the sensitivity of the design performance to variability. The calibration and the verification of the prediction are based on 130nm devices. Projection to future nano-scaled technology nodes indicates that further scaling requires good modeling of the parametric variations to overcome poor yield, unless the variations can be better controlled.