Accelerated Flexible Processor Architecture for Crypto Information

With the growth of the information technology, cryptographic processing as a vehicle for secure communication has been indispensable in almost all application systems. Therefore, efficient cryptographic processing will become increasingly vital to good system performance. In this thesis, we explore hardware/software design techniques to improve the performance and flexibility of crypt information, including symmetric-key cipher algorithms and Hash functions, and a processor architecture is put forward. As to crypto units, we adopt a specific design which is reconfigurable. At the mean time, a set of new VLIW instructions that improve the efficiency of the analyzed algorithms are introduced. A number of algorithms were implemented on an architectural simulator and dedicated parts of the architecture were realized using Verilog to measure hardware parameters.