Title :
The application of BT-FinFET technology for sub 60nm DRAM integration
Author :
Choong-Ho Lee ; Yoon, Choong-Ho Lee Jae-Man ; Lee, Chul ; Kim, Keunnam ; Park, Seung Bae ; Young Joon Ann ; Kang, Hee Soo ; Park, Donggun
Author_Institution :
R&D Center, Samsung Electron., Yongin, South Korea
Abstract :
In this paper, the application of body tied FinFET is presented for a technology breakthrough beyond sub 60nm. DRAM on bulk Si substrate has been successfully integrated and the characteristics were compared to recess channel and planar cell array transistor DRAM. We present a comparison of three different device structures and show damascene BT-FinFET using NWL (negative word line) scheme with low channel for a highly manufacturable DRAM for sub 60nm technology node.
Keywords :
DRAM chips; cellular arrays; field effect transistors; integrated circuit design; memory architecture; silicon; 60 nm; BT-FinFET technology; DRAM; negative word line scheme; planar cell array transistor; recess channel array transistor; Capacitors; Doping; FinFETs; Immune system; Leakage current; MOSFET circuits; Manufacturing; Oxidation; Random access memory; Transistors;
Conference_Titel :
Integrated Circuit Design and Technology, 2005. ICICDT 2005. 2005 International Conference on
Print_ISBN :
0-7803-9081-4
DOI :
10.1109/ICICDT.2005.1502585
