Strategies to cope with plasma charging damage in design and layout phases

Author

Wang, Z. ; Ackaert, J. ; Scarpa, A. ; Salm, C. ; Kuper, F.G. ; Vugts, M.

Author_Institution

Res. Inst., Twente Unv., Enschede, Netherlands

fYear

2005

fDate

9-11 May 2005

Firstpage

91

Lastpage

98

Abstract

In this paper, strategics to cope with plasma charging damage in design and layout phases are discussed. A semi-empirical model is addressed first. With this model, a designer is able to predict the plasma charging induced yield loss of the circuit, if the antenna ratio (AR) distribution of the circuit is available. Then a novel first order self-balancing interconnect layout design is proposed to reduce the plasma charging damage. Moreover, the temperature effect on the protection diode is discussed and a strategic diode protection scheme for plasma charging damage is proposed. In addition to these general methods, a set of design rules is given to protect floating metal-insulator-metal (MIM) capacitors from plasma charging damage.

Keywords

MIM devices; capacitors; integrated circuit layout; integrated circuit modelling; integrated circuit yield; plasma materials processing; antenna ratio distribution; diode protection scheme; metal-insulator-metal capacitor; plasma charging damage; self-balancing interconnect layout; semi-empirical model; temperature effect; Circuits; Metal-insulator structures; Plasma applications; Plasma devices; Plasma materials processing; Plasma measurements; Plasma sources; Plasma temperature; Protection; Semiconductor diodes;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology, 2005. ICICDT 2005. 2005 International Conference on

Print_ISBN

0-7803-9081-4

Type

conf

DOI

10.1109/ICICDT.2005.1502600

Filename

1502600