• DocumentCode
    1893216
  • Title

    Assertion clustering for compacted test sequence generation

  • Author

    Tong, Jason G. ; Boule, Marc ; Zilic, Zeljko

  • Author_Institution
    Integrated Microsyst. Lab., McGill Univ., Montréal, QC, Canada
  • fYear
    2012
  • fDate
    19-21 March 2012
  • Firstpage
    694
  • Lastpage
    701
  • Abstract
    Assertions are now widely used in verification as a means to help convey designer intent (as specification snippets) and also to simplify the detection of erroneous conditions by the firing of assertions. With this expressive modeling power, assertions can also be used for different tasks, such as helping to assess test coverage and even as a source for test generation. Our work deals with this last aspect, namely assertion based test generation. In this paper, we present our compacted test generation strategy based on assertions. Our compaction approach is experimentally evaluated using nearly three hundred assertions to show the amount of reduction that can be obtained in the size of the test sets. This ultimately has a positive impact on verification time, in the quest for bug free designs.
  • Keywords
    automatic test pattern generation; integrated circuit design; integrated circuit testing; assertion based test generation; assertion clustering; bug free design; compacted test sequence generation strategy; digital integrated circuit design; erroneous conditions detection; expressive modeling power; test coverage assessment; Automata; Clustering algorithms; Clustering methods; Compaction; Generators; Hardware; Vectors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality Electronic Design (ISQED), 2012 13th International Symposium on
  • Conference_Location
    Santa Clara, CA
  • ISSN
    1948-3287
  • Print_ISBN
    978-1-4673-1034-5
  • Type

    conf

  • DOI
    10.1109/ISQED.2012.6187567
  • Filename
    6187567