An enhanced debug-aware network interface for Network-on-Chip

As emerging System on Chips (SoCs) tend to have many cores, the interactions among cores through functional interconnects such as bus or Network on Chips (NoCs) are becoming complex. The increase in complexity of IP blocks and on-chip communication has accentuated the need to enhance traditional debug methods for SoCs. In this paper, we propose a new debug aware Network Interface (NI). The proposed debug aware NI monitors the transactions issued by processing elements and extracts the global order of transactions from the local partial order of transactions. Moreover, the proposed interface provides a mechanism for a cross-triggers debugging. The modules in charge of cross-trigger debugging monitor the transactions issued by connected IP blocks and invoke appropriate debug operations at the right time. Trace data and trigger events are extracted and routed to Shared Direct Memory Access Unit (SDMAU). SDMAU combines debug traces from different NIs. The major benefits of using our proposed mechanism over traditional techniques are as follows: 1) the proposed debug aware NI can generate non-intrusively the global states of a system that involve multiple clock domains and enable validation of global properties, 2) It can detect, mark and bypass severe faulty conditions such as deadlocks resulting from design errors or electrical faults in real time, 3) SDMAU maintains an efficient transfer of trace data to an external memory and there is no need for a large internal trace memory.