Resynthesis of sequential circuits for low power

At the logic level, a popular approach is to power down the sequential machine during the self-loops of the underlying finite state machine (FSM). In this work, we extend this idea to resynthesize existing sequential circuits to reduce power. We report a novel technique based on symbolic simulation of a sequential circuit to extract its self-loops without extracting the corresponding state transition diagram (STG). Since self loops may not be inherently present in the corresponding FSM, we partition the circuit heuristically and identify partial-self-loops for each partition to bring down the corresponding sub-circuit by gating the clock sub-tree feeding that partition. By using this approach, we could save up to 45% of the total power on a controller circuit of a microprocessor design, where traditional techniques could not save any power